# MIPS Single-Cycle Datapath ![](https://cdn.hashnode.com/res/hashnode/image/upload/v1724824551177/a7540ec7-7f6b-4d51-9b46-199b721aaef2.png align="center") The single-cycle data path for MIPS in the image includes various control signals that govern how the data path components operate during the execution of an instruction. Here's a description of each control signal: 1. **RegDst**: This signal controls which register is written to in the register file. If `RegDst` is 0, the destination register is `rt` (field \[20-16\]). If `RegDst` is 1, the destination register is `rd` (field \[15-11\]). This is used in instructions like `R-type` (e.g., `add, sub`) versus `I-type` (e.g., `lw, sw`). 2. **Branch**: This signal determines whether a branch instruction is being executed. If `Branch` is 1 and the `Zero` signal from the ALU is also 1, it indicates that a branch condition is met, and the PC will be updated to the branch target address. It is used with branch instructions like `beq`. 3. **MemRead**: This signal enables reading from the data memory. If `MemRead` is 1, data memory is read during the current clock cycle. This is used for `load` instructions (`lw`). 4. **MemtoReg**: This signal controls whether the data to be written to the register file comes from the ALU result or the data memory. If `MemtoReg` is 0, the ALU result is written to the register file. If `MemtoReg` is 1, data read from memory is written to the register file. It is used for distinguishing between `lw` (load word) and `R-type` instructions. 5. **ALUOp**: This is a multi-bit control signal that specifies the operation the ALU should perform. The specific ALU operation depends on the instruction type (e.g., `add, sub, and, or`). 6. **MemWrite**: This signal controls writing to the data memory. If `MemWrite` is 1, data is written to the memory location specified by the address input during the current clock cycle. This is used for `store` instructions (`sw`). 7. **ALUSrc**: This signal determines the second operand for the ALU. If `ALUSrc` is 0, the second operand is the data read from the second register (`Read data 2`). If `ALUSrc` is 1, the second operand is the sign-extended immediate value (used in `I-type` instructions). 8. **RegWrite**: This signal controls writing to the register file. If `RegWrite` is 1, the register file is updated with the result of the operation (either from the ALU result or memory). This is used in instructions that modify registers, such as `R-type` instructions and `lw`. 9. **Zero**: This signal is an output from the ALU that indicates if the result of the ALU operation is zero. It is primarily used for the `Branch` control logic. 10. **Shift left 2**: This is not a control signal per se but a shift operation that is applied to the 16-bit immediate field of a branch instruction to calculate the branch target address. 11. **PCSrc** (implied by the `Branch` and `Zero` signals): This signal determines the source of the next PC value. If the `Branch` signal is active and the `Zero` signal from the ALU is high, the `PCSrc` will select the branch target address; otherwise, it selects `PC + 4`. ![](https://cdn.hashnode.com/res/hashnode/image/upload/v1724824714240/c8e8689e-610b-462c-b56c-edb7a62e3b7c.png align="center") The table provided shows the control signal settings for various MIPS instruction types in the single-cycle data path. This table helps understand how the control signals are configured for different types of instructions to ensure the correct operation of the processor. Let’s go through the table row by row: **1\. R-format Instructions (add, sub, and, or, slt)** * **RegDst**: `1` * This signal is set to `1` for R-format instructions, indicating that the destination register is the `rd` field (bits \[15-11\] of the instruction). * **ALUSrc**: `0` * For R-format instructions, the second ALU operand comes from the register file (`Read data 2`), not from an immediate value. Hence, `ALUSrc` is set to `0`. * **MemtoReg**: `0` * Since R-format instructions do not involve memory operations, the value written to the register comes from the ALU result. Thus, `MemtoReg` is set to `0`. * **RegWrite**: `1` * R-format instructions write the result back to a register, so `RegWrite` is set to `1`. * **MemRead**: `0` * No memory read operation is required for R-format instructions, so `MemRead` is `0`. * **MemWrite**: `0` * Similarly, there is no memory write operation in R-format instructions, so `MemWrite` is `0`. * **Branch**: `0` * R-format instructions do not involve branching, so the `Branch` signal is set to `0`. * **ALUOp**: `10` * For R-format instructions, the `ALUOp` is set to `10` to indicate that the specific ALU operation is determined by the `funct` field of the instruction. This field provides the details about whether the operation is `add`, `sub`, `AND`, `OR`, or `slt`. **2\. Load Word (lw)** * **RegDst**: `0` * For `lw` (load word) instructions, the destination register is the `rt` field (bits \[20-16\] of the instruction). Therefore, `RegDst` is set to `0`. * **ALUSrc**: `1` * `lw` instructions use an immediate offset to calculate the memory address, so the second ALU operand should be the sign-extended immediate value. Thus, `ALUSrc` is `1`. * **MemtoReg**: `1` * The data loaded from memory must be written to the register file. Hence, `MemtoReg` is set to `1` to indicate that the data to be written to the register file comes from memory. * **RegWrite**: `1` * The `lw` instruction writes the data fetched from memory into a register, so `RegWrite` is `1`. * **MemRead**: `1` * Memory read is required to fetch the data, so `MemRead` is set to `1`. * **MemWrite**: `0` * `lw` does not write to memory; it only reads. Therefore, `MemWrite` is `0`. * **Branch**: `0` * `lw` is not a branch instruction, so `Branch` is `0`. * **ALUOp**: `00` * For `lw` instructions, the ALU is used to compute the address by performing an addition, so `ALUOp` is set to `00` (which represents an addition operation). **3\. Store Word (sw)** * **RegDst**: `X` (Don't care) * For `sw` (store word) instructions, there is no destination register for the result. Therefore, the `RegDst` value is a "don't care" (`X`). * **ALUSrc**: `1` * `sw` instructions also use an immediate offset to calculate the memory address, so the second ALU operand is the sign-extended immediate. Thus, `ALUSrc` is `1`. * **MemtoReg**: `X` (Don't care) * `MemtoReg` is irrelevant for `sw` because no register is written (`RegWrite` is `0`). Therefore, it is marked as `X`. * **RegWrite**: `0` * The `sw` instruction does not write to any register, so `RegWrite` is `0`. * **MemRead**: `0` * `sw` does not require reading from memory, hence `MemRead` is `0`. * **MemWrite**: `1` * `sw` involves writing data to memory, so `MemWrite` is set to `1`. * **Branch**: `0` * `sw` is not a branch instruction, so `Branch` is `0`. * **ALUOp**: `00` * Similar to `lw`, the ALU in `sw` instructions performs an addition to calculate the memory address, hence `ALUOp` is `00`. **4\. Branch on Equal (beq)** * **RegDst**: `X` (Don't care) * For `beq` (branch if equal) instructions, there is no destination register. Therefore, `RegDst` is a "don't care" (`X`). * **ALUSrc**: `0` * `beq` instructions use two register values to determine equality. Therefore, both ALU operands are taken from registers (`Read data 1` and `Read data 2`), setting `ALUSrc` to `0`. * **MemtoReg**: `X` (Don't care) * `MemtoReg` is irrelevant for `beq` because no register is written (`RegWrite` is `0`), so it is marked as `X`. * **RegWrite**: `0` * The `beq` instruction does not write to any register, so `RegWrite` is `0`. * **MemRead**: `0` * `beq` does not involve memory read, hence `MemRead` is `0`. * **MemWrite**: `0` * `beq` does not involve memory write, so `MemWrite` is `0`. * **Branch**: `1` * `beq` is a branch instruction, so `Branch` is set to `1`. * **ALUOp**: `01` * For `beq` instructions, the ALU must perform a subtraction to check if the two operands are equal (`result` is zero). Thus, `ALUOp` is set to `01`. ### What does the ALU do and what tells it what to do? ![](https://cdn.hashnode.com/res/hashnode/image/upload/v1724830530027/573535d5-d35b-4761-bab4-c8bd58d4e6a7.png align="center") The table provides details about how the ALU (Arithmetic Logic Unit) operates based on different instruction types in a MIPS processor. It outlines the relationship between the instruction opcode, the ALUOp signal from the control unit, the `funct` field for R-type instructions, the desired ALU operation, and the specific control signals sent to the ALU. 1. **Instruction Opcode**: * This is a 6-bit field `[31:26]` in the instruction that specifies the basic type of instruction (e.g., `load word`, `store word`, `branch equal`, or `R-type` operations). * The opcode is decoded by the control unit to generate the appropriate control signals, including `ALUOp`. 2. **ALUOp**: * `ALUOp` is a 2-bit control signal output by the control unit. * It provides a coarse indication of what type of operation the ALU should perform. * `ALUOp` has three primary settings: * `00` for `load word (lw)` and `store word (sw)` instructions, indicating an addition operation for address calculation. * `01` for `branch equal (beq)` instructions, indicating a subtraction operation to check for equality. * `10` for `R-type` instructions, indicating that the specific ALU operation should be determined by the `funct` field (`[5:0]`). 3. **Instruction Operation**: * This column provides the human-readable description of the instruction (e.g., `load word`, `store word`, `add`, `subtract`). 4. **Funct Field**: * For `R-type` instructions, the `funct` field (`[5:0]` bits of the instruction) provides additional information to specify the exact operation to perform. * The `funct` field works in conjunction with the `ALUOp` signal to determine the precise operation of the ALU (e.g., `add`, `subtract`, `AND`, `OR`, `set on less than`). * The `funct` field is only relevant when `ALUOp` is `10`. 5. **Desired ALU Action**: * This column specifies the actual operation that the ALU is expected to perform (e.g., `add`, `subtract`, `AND`). 6. **ALU Control Input**: * This is a 4-bit control signal sent to the ALU to dictate the specific operation to execute. * The ALU Control input is derived from both the `ALUOp` and, if applicable, the `funct` field. * Different values of the ALU Control input correspond to different operations: * `0010` for `add` * `0110` for `subtract` * `0000` for `AND` * `0001` for `OR` * `0111` for `set on less than` **How the ALU is Controlled** 1. **Control Unit and ALUOp**: * The control unit uses the opcode `[31:26]` from the instruction to determine the general type of instruction. * Based on this opcode, the control unit sets the `ALUOp` signal: * `00` if the instruction is `lw` or `sw` (requiring an addition to compute memory addresses). * `01` if the instruction is `beq` (requiring a subtraction to compare registers). * `10` if the instruction is `R-type` (using the `funct` field to specify the exact operation). 2. **ALU Control Unit**: * The ALU Control unit receives both the `ALUOp` from the control unit and, if necessary, the `funct` field `[5:0]` for `R-type` instructions. * If `ALUOp` is `00` or `01`, the ALU Control directly interprets this to set the ALU operation to `add` (`0010`) or `subtract` (`0110`). * If `ALUOp` is `10`, the ALU Control examines the `funct` field to determine the specific operation: * `100000` (add) maps to `0010`. * `100010` (subtract) maps to `0110`. * `100100` (AND) maps to `0000`. * `100101` (OR) maps to `0001`. * `101010` (set on less than) maps to `0111`. **Examples from the Table** * **LW (Load Word)**: * Opcode: `[31:26] = 100011` * `ALUOp = 00` (indicating add operation for address calculation) * Desired ALU action: `add` * ALU control input: `0010` * **SW (Store Word)**: * Opcode: `[31:26] = 101011` * `ALUOp = 00` (similar to `lw` for address calculation) * Desired ALU action: `add` * ALU control input: `0010` * **Branch Equal (beq)**: * Opcode: `[31:26] = 000100` * `ALUOp = 01` (indicating subtract operation to check equality) * Desired ALU action: `subtract` * ALU control input: `0110` * **R-type (e.g., Add, Subtract, AND, OR, Set on Less Than)**: * Opcode: `[31:26] = 000000` (indicating an R-type instruction) * `ALUOp = 10` (indicating that the `funct` field should determine the operation) * Funct field specifies the exact operation (e.g., `100000` for add, `100010` for subtract) * Desired ALU action depends on the `funct` field: * Add: ALU control input `0010` * Subtract: ALU control input `0110` * AND: ALU control input `0000` * OR: ALU control input `0001` * Set on less than: ALU control input `0111` ### R-type (add, etc.) ![](https://cdn.hashnode.com/res/hashnode/image/upload/v1724826173343/4adba174-824d-4e41-91fd-8ac9dea158ed.png align="center") The data path provided is specific to executing R-type instructions (e.g., `add`, `sub`, `AND`, `OR`, `slt`) in a MIPS processor. **Step-by-Step Execution of R-type Instructions** 1. **Instruction Fetch**: * The **Program Counter (PC)** holds the address of the next instruction to be executed. * The instruction at the address pointed to by the PC is fetched from the **Instruction Memory**. * The instruction is loaded into the instruction register, and the PC is incremented by 4 to point to the next instruction (since MIPS instructions are 4 bytes). 2. **Instruction Decode**: * The fetched instruction is divided into several fields: * `op` (opcode) is in bits \[31-26\]. * `rs` (source register 1) is in bits \[25-21\]. * `rt` (source register 2) is in bits \[20-16\]. * `rd` (destination register) is in bits \[15-11\]. * `shamt` (shift amount, used in shift instructions) is in bits \[10-6\]. * `funct` (function code for specific R-type operations) is in bits \[5-0\]. * The **Control Unit** reads the `op` field. For R-type instructions, `op` is always `000000`, signaling the Control Unit to set control signals for R-type execution. 3. **Read Registers**: * The `rs` and `rt` fields are used as addresses to read two registers (`Read register 1` and `Read register 2`) from the **Register File**. * The values stored in these registers are output as `Read data 1` and `Read data 2`. 4. **Execute**: * The ALU (Arithmetic Logic Unit) performs the operation specified by the `funct` field of the instruction. * The **ALU Control** unit determines the specific operation (`add`, `sub`, `AND`, `OR`, `slt`) based on the `funct` field. * `ALUSrc` control signal is set to `0` for R-type instructions, indicating that the second operand for the ALU comes from `Read data 2` (the second register operand), not an immediate value. * The ALU receives two inputs: `Read data 1` and `Read data 2`. * The ALU performs the desired operation and outputs the result. 5. **Write Back**: * The result from the ALU is written back to the register file. * The `RegDst` control signal is set to `1` for R-type instructions, indicating that the destination register (`Write register`) is determined by the `rd` field (bits \[15-11\]). * `RegWrite` is set to `1`, enabling writing the ALU result back to the register specified by `rd`. * The result of the ALU operation is stored in the register file at the address specified by the `rd` field. 6. **Update Program Counter**: * Since R-type instructions are not branch instructions, the next PC is simply `PC + 4`, which was already computed during the instruction fetch stage. * The MUX that determines the next PC value selects the output that adds 4 to the current PC, as `Branch` is `0` and `Zero` from the ALU does not affect the PC. **Control Signals Specific to R-type Instructions:** * **RegDst = 1**: The destination register is determined by the `rd` field. * **ALUSrc = 0**: The second ALU operand comes from the register `rt` (`Read data 2`). * **MemtoReg = 0**: The data to be written to the register comes from the ALU output, not from memory. * **RegWrite = 1**: Enables writing back to the register file. * **MemRead = 0**: No read operation from data memory is performed. * **MemWrite = 0**: No write operation to data memory is performed. * **Branch = 0**: No branching is performed. * **ALUOp = 10**: The ALU operation is specified by the `funct` field of the instruction. ### Load (lw) ![](https://cdn.hashnode.com/res/hashnode/image/upload/v1724826356781/a3a29269-9aea-460a-907c-55894293de9d.png align="center") The provided data path illustrates the execution of a `load word (lw)` instruction in a MIPS processor. **Step-by-Step Execution of the** `lw` **(Load Word) Instruction** 1. **Instruction Fetch**: * The **Program Counter (PC)** contains the address of the instruction to be fetched. * The **Instruction Memory** reads the instruction located at the address specified by the PC. This instruction is fetched into the instruction register. * The PC is then incremented by 4 (since MIPS instructions are 4 bytes) to point to the next instruction. 2. **Instruction Decode**: * The fetched instruction is decoded, and different fields of the instruction are extracted: * `op` (opcode) is in bits \[31-26\]. * `rs` (base register) is in bits \[25-21\]. * `rt` (destination register) is in bits \[20-16\]. * `immediate` (offset) is in bits \[15-0\]. * The **Control Unit** reads the `op` field. For the `lw` instruction, the opcode is `100011`, which signals the Control Unit to set control signals accordingly. 3. **Read Registers**: * The base register address (`rs`) is used to read the content of the source register from the **Register File**. The data read from the base register (`Read data 1`) is used as the base address for memory access. * The `rt` register is the target register where the loaded data will be written. Although the `rt` register is specified, it is not read at this stage; rather, it is used later during the write-back stage. 4. **Calculate Memory Address**: * The `immediate` field is sign-extended from 16 bits to 32 bits to handle the offset correctly. * The **ALU** performs an addition operation to calculate the effective memory address: * First Operand: The base address obtained from `Read data 1` (the content of the base register `rs`). * Second Operand: The sign-extended immediate value (offset). * The **ALUSrc** control signal is set to `1` for `lw` instructions, indicating that the ALU should use the sign-extended immediate value as the second operand. 5. **Memory Access**: * The calculated address from the ALU output is used to access the **Data Memory**. * The **MemRead** control signal is set to `1` to enable reading from data memory. * The data at the calculated address is read from the memory and stored in the `Read data` output of the Data Memory component. 6. **Write Back**: * The data read from the memory is written back to the destination register (`rt`). * The **MemtoReg** control signal is set to `1`, indicating that the data to be written to the register comes from the memory (not from the ALU result). * The **RegDst** control signal is set to `0`, specifying that the destination register is defined by the `rt` field of the instruction (bits \[20-16\]). * The **RegWrite** control signal is set to `1` to enable writing the data into the register file. * The data from the `Read data` output of the Data Memory is written into the register specified by the `rt` field. 7. **Update Program Counter**: * As the `lw` instruction is not a branch instruction, the next PC is set to `PC + 4`. * The MUX that controls the next PC value selects the incremented PC (`PC + 4`), as the `Branch` control signal is `0`. **Control Signals Specific to** `lw` **Instructions:** * **RegDst = 0**: The destination register is specified by the `rt` field. * **ALUSrc = 1**: The second operand for the ALU comes from the sign-extended immediate value. * **MemtoReg = 1**: The data to be written to the register comes from memory (not from the ALU). * **RegWrite = 1**: Enables writing to the register file. * **MemRead = 1**: Enables reading from data memory. * **MemWrite = 0**: No write operation to data memory is performed. * **Branch = 0**: No branching is performed. * **ALUOp = 00**: The ALU is set to perform an addition operation to compute the memory address. ### Branch on Equal (beq) ![](https://cdn.hashnode.com/res/hashnode/image/upload/v1724826882945/2f231169-fbbb-405c-a9d5-04ecfea1dc99.png align="center") The provided data path illustrates the execution of a `branch on equal (beq)` instruction in a MIPS processor. **Step-by-Step Execution of the** `beq` **(Branch on Equal) Instruction** 1. **Instruction Fetch**: * The **Program Counter (PC)** contains the address of the instruction to be executed. * The instruction located at the address specified by the PC is fetched from the **Instruction Memory**. This instruction is loaded into the instruction register. * Simultaneously, the PC is incremented by 4 to point to the next sequential instruction (since MIPS instructions are 4 bytes long). 2. **Instruction Decode**: * The fetched instruction is decoded, and different fields of the instruction are extracted: * `op` (opcode) is in bits \[31-26\]. * `rs` (first source register) is in bits \[25-21\]. * `rt` (second source register) is in bits \[20-16\]. * `immediate` (branch offset) is in bits \[15-0\]. * The **Control Unit** reads the `op` field. For the `beq` instruction, the opcode is `000100`, which signals the Control Unit to set control signals for a branch operation. 3. **Read Registers**: * The `rs` and `rt` fields are used to read two registers from the **Register File**. * The data in these registers (`Read data 1` and `Read data 2`) are the two operands that will be compared to determine if the branch should be taken. 4. **Compute Branch Target Address**: * The `immediate` field, which represents the offset for the branch, is sign-extended from 16 bits to 32 bits to handle the full address range. * The sign-extended immediate value is then shifted left by 2 bits (to account for the 4-byte alignment of instructions) to create the final branch offset. * The branch target address is calculated by adding this shifted offset to the incremented PC (`PC + 4`). This addition is performed by an adder separate from the main ALU, depicted as "Add" in the diagram. 5. **Evaluate Branch Condition**: * The ALU performs a subtraction operation between `Read data 1` and `Read data 2` to check for equality. * The **ALU Control** signal for `beq` is set to perform a subtraction operation (`ALUOp = 01`). * If the result of the subtraction is zero, the `Zero` output from the ALU is set to 1, indicating that the two operands are equal. 6. **Update Program Counter (PC)**: * The **Branch** control signal is set to `1` for the `beq` instruction. * The `PCSrc` signal is derived from the logical AND of the `Branch` control signal and the `Zero` signal from the ALU. * If `Zero` is 1 (indicating that `Read data 1` is equal to `Read data 2`) and `Branch` is 1, then the `PCSrc` signal becomes 1, causing the PC to be updated to the branch target address calculated earlier. * If the branch condition is not met (`Zero` is 0), the PC is updated to `PC + 4` (the next sequential instruction). **Control Signals Specific to** `beq` **Instructions:** * **RegDst = X**: Not used in `beq` since there is no register write-back. * **ALUSrc = 0**: Both operands for the ALU come from the register file (`Read data 1` and `Read data 2`). * **MemtoReg = X**: Not used in `beq` since there is no data transfer to a register. * **RegWrite = 0**: No register is written during a `beq` instruction. * **MemRead = 0**: No memory read operation is performed. * **MemWrite = 0**: No memory write operation is performed. * **Branch = 1**: Indicates that this is a branch instruction. * **ALUOp = 01**: The ALU performs a subtraction operation to compare the two registers. ### Jump (j) ![](https://cdn.hashnode.com/res/hashnode/image/upload/v1724827056275/90e41a9d-8448-4a00-83e9-324f8910a233.png align="center") The provided data path illustrates the execution of a `jump (j)` instruction in a MIPS processor. **Step-by-Step Execution of the** `j` **(Jump) Instruction** 1. **Instruction Fetch**: * The **Program Counter (PC)** holds the address of the current instruction to be executed. * The instruction at the address specified by the PC is fetched from the **Instruction Memory**. This instruction is loaded into the instruction register. * Concurrently, the PC is incremented by 4 to point to the next instruction (since each MIPS instruction is 4 bytes long). 2. **Instruction Decode**: * The fetched instruction is decoded, and the following fields are extracted: * `op` (opcode) is in bits \[31-26\]. * `address` (jump target address) is in bits \[25-0\]. * The **Control Unit** reads the `op` field. For the `j` (jump) instruction, the opcode is `000010`, which signals the Control Unit to set control signals accordingly. 3. **Compute Jump Target Address**: * The `address` field, which provides the jump target, is shifted left by 2 bits. This shifting accounts for the 4-byte alignment of instructions in MIPS. * The upper 4 bits of the new PC (`PC + 4`) are retained (bits \[31-28\]), while the lower 28 bits are filled with the shifted `address` field. This forms the complete 32-bit jump target address (`Jump address`). 4. **Update Program Counter (PC)**: * The **Jump** control signal is set to `1` for the `j` instruction. * The MUX that determines the next value of the PC selects the jump address when the **Jump** signal is `1`. * The new PC is thus updated to the calculated jump address, redirecting the flow of control to the target address specified by the jump instruction. * No other operations, such as register or memory read/write, are performed since the `j` instruction only alters the program control flow. **Control Signals Specific to** `j` **Instructions:** * **RegDst = X**: Not used in `j` since no register write-back is involved. * **ALUSrc = X**: Not used in `j` since no ALU operation is performed. * **MemtoReg = X**: Not used in `j` since no data transfer to a register occurs. * **RegWrite = 0**: No register is written during a `j` instruction. * **MemRead = 0**: No memory read operation is performed. * **MemWrite = 0**: No memory write operation is performed. * **Branch = 0**: Not a branch instruction. * **Jump = 1**: Indicates that this is a jump instruction. * **ALUOp = XX**: Irrelevant for `j` since no ALU operation is needed. ### Store (sw) The provided data path illustrates the execution of a `store word (sw)` instruction in a MIPS processor. Let's go through the execution steps for the `sw` instruction in detail: **Step-by-Step Execution of the** `sw` **(Store Word) Instruction** 1. **Instruction Fetch**: * The **Program Counter (PC)** contains the address of the instruction to be fetched. * The **Instruction Memory** reads the instruction located at the address specified by the PC. This instruction is loaded into the instruction register. * Simultaneously, the PC is incremented by 4 to point to the next sequential instruction (since MIPS instructions are 4 bytes). 2. **Instruction Decode**: * The fetched instruction is decoded, and different fields of the instruction are extracted: * `op` (opcode) is in bits \[31-26\]. * `rs` (base register) is in bits \[25-21\]. * `rt` (source register for data to be stored) is in bits \[20-16\]. * `immediate` (offset) is in bits \[15-0\]. * The **Control Unit** reads the `op` field. For the `sw` instruction, the opcode is `101011`, which signals the Control Unit to set control signals for a store operation. 3. **Read Registers**: * The base register address (`rs`) is used to read the content of the base register from the **Register File**. The data read from the base register (`Read data 1`) is used as the base address for memory access. * The `rt` register contains the data that will be stored in memory. The data read from the `rt` register (`Read data 2`) will be the data written to the memory. 4. **Calculate Memory Address**: * The `immediate` field is sign-extended from 16 bits to 32 bits to handle the offset correctly. * The **ALU** performs an addition operation to calculate the effective memory address: * First Operand: The base address obtained from `Read data 1` (the content of the base register `rs`). * Second Operand: The sign-extended immediate value (offset). * The **ALUSrc** control signal is set to `1` for `sw` instructions, indicating that the ALU should use the sign-extended immediate value as the second operand. 5. **Memory Access**: * The calculated address from the ALU output is used to access the **Data Memory**. * The **MemWrite** control signal is set to `1` to enable writing to data memory. * The data from `Read data 2` (the content of the `rt` register) is written to the calculated memory address. * The **MemRead** control signal is `0` since no memory read operation is required. 6. **Write Back**: * There is no write-back stage for the `sw` instruction because it does not modify any register values. * The data path ends after the memory write operation. 7. **Update Program Counter (PC)**: * As the `sw` instruction is not a branch instruction, the next PC is set to `PC + 4`. * The MUX that controls the next PC value selects the incremented PC (`PC + 4`), as the `Branch` control signal is `0`. **Control Signals Specific to** `sw` **Instructions:** * **RegDst = X**: Not used in `sw` since there is no register write-back. * **ALUSrc = 1**: The second operand for the ALU comes from the sign-extended immediate value. * **MemtoReg = X**: Not used in `sw` since no data is transferred to a register. * **RegWrite = 0**: No register is written during an `sw` instruction. * **MemRead = 0**: No memory read operation is performed. * **MemWrite = 1**: Enables writing to data memory. * **Branch = 0**: No branching is performed. * **ALUOp = 00**: The ALU is set to perform an addition operation to compute the memory address.